Dielectric planarization has become extremely important for multilevel interconnection of very large scale integrated (VLSI) circuits as device geometries have become smaller and circuit densities have become higher. See, for example, A. C. Adams and C. D. Capio, Journal of Electrochemical Society, Vol. 128, 1981, pp. 423. With smaller geometries, the planarization of dielectric layers in multilevel interconnects requires two stages: interlevel dielectric gap filling, and subsequent local or global planarization. The present invention is concerned only with gap filling, and in particular with a high throughput gap filling process.
Referring to FIG. 1, there are shown two closely spaced metal lines on a silicon substrate. The metal lines are separated by a lateral distance of .DELTA.X, and have a height of .DELTA.Y. The space between the metal lines is called a "gap", having an aspect ratio defined as .DELTA.Y/.DELTA.X. After depositing and defining the metal interconnection lines of a semiconductor circuit, it is usually necessary to fill the gaps between interconnection lines, and to cover the entire interconnect layer with silicon oxide before proceeding with the next manufacturing step. Filling such gaps, without creating voids in which no oxide is deposited, becomes increasingly difficult as the gap width becomes smaller than one micron and as the aspect ratio increases above a value of 1.0 Voids are undesirable because they can contribute to electrical shorts and long term device reliability problems.
Current techniques in plasma enhanced chemical vapor deposition (PECVD) employ a sequence of deposition, etch and deposition steps for good quality interlevel dielectric (ILD) gap filling, without void formation, for interconnect spaces smaller than 1.0 microns and aspect ratios greater than unity. The prior art deposition/etch/deposition sequence typically requires three to four process chambers to accomplish good quality oxide ILD gap fill, and therefore has low throughput. As device geometries shrink below 0.6 micron, it has been found that the prior art deposition/etch/deposition sequence is unable to satisfactorily fill ILD gaps at sufficient water throughput.
Biased electron cyclotron resonance (ECR) plasma deposition technology has been demonstrated to gap fill and planarize small spaces at high aspect ratios (e.g., aspect ratios of 2.0 and higher). Biased ECR deposition yields high quality oxide films. The principles of ECR plasma technology are described by J. Asmussen, J. Vacuum Science Technology A, Vol. 7, No. 3, May/June 1989, p. 883, which is hereby incorporated by reference as background information. Published articles which describe prior art biased ECR deposition technology including (1) S. Matsuo and M. Kiuchi, Japan Journal of Applied Physics, Vol. 22, No. 4, April 1983, p. L210, and (2) D. R. Dennison, C. Chiang, and D. Fraser, Ext. Abstracts, 175th ECS Meeting, Los Angeles, Vol. 89-1, Spring 1989, p. 261.
The major shortcomings of biased ECR deposition have been (1) low deposition rates (under about 1500 Angstroms/min), and (2) high compressive film stress (typically greater than 3.times.10.sup.9 dynes/cm.sup.2. Low deposition rates make biased ECR deposition unacceptably expensive for large scale semiconductor manufacturing, and high film stress can lead to device failures. The present invention overcomes both of these problems.